1. Technical Field
The invention relates generally to circuit design evaluation, and more particularly, to forming a statistical model of independently variable parameters for timing analysis.
2. Background Art
All integrated circuit (IC) manufacturing lines are subject to random variation in process conditions that cause random variation in the chips produced. Chips of the same design will differ in geometry in random ways across processing from chip-to-chip, and geometries of the same design will differ in random ways across a single chip. In order to ensure that a design will function correctly when manufactured, the designer needs to simulate the range of variations expected during the design process. For example, referring to FIG. 1, wire resistance and capacitance depends on: a) the vertical geometry parameters describing the stack heights, especially wire thickness (t) and insulator or via thicknesses (ha or hb), and b) the lateral geometry parameters like wire width (w) and spacing (d) to neighboring wires. Tolerances in width and thickness are the main contributors to process variation of interconnect resistance and capacitance. These parameters are independent.
Statistical timing analysis needs to include simulation of the tolerances of these independent parameters for every wire level. Typically, statistical timing analysis employs a statistical distribution of variations for each parameter, and then analyzes wire delay and circuit performance based on the statistical distributions of variations for each parameter. Accordingly, the more parameters that must be characterized and analyzed, the more cumbersome the task becomes. Conventionally, a large number of geometries need to be evaluated. For example, for a 6 level metal technology, 24 independent timing parameters and 2^24 geometries require evaluation. This number of evaluations is an impossible burden for the timing tool. Also, every metal level simulation has to be performed for nine geometries, e.g., narrow-thin, narrow-thick, wide-thin, wide-thick, each with thick and thin isolator stack and target. This situation changes the regular evaluation (e.g., Spice) file into a file with nine values for every element, significantly increasing the size of the extracted netlist, and costing additional giga-bytes of fast access storage.
One conventional approach to address simulation tolerances in timing analysis includes selecting a set of geometries that bound the process variation distributions. The simulation tolerances include, for example, a target width and maximum changes in width (tracking with space to the neighboring wires) within the boundaries of the width variations, and a target thickness and maximum changes in thickness within the boundaries of the thickness variations. That is, current simulations use: best condition (BC), nominal (NOM) and worst condition (WC) for each wire geometry. All vertical and horizontal dimensions, as shown in FIG. 1, are scaled together with the same relation up to the standard deviation multiple (e.g., 3sigma). This scaling direction sets the parameter varying methodology. The timing tool used to analyze the circuit design assumes linear scaling between the simulated values, i.e., capacitance, resistance and inductance, with the parameter varying methodology. Across chip variation (ACV) of width and thickness require a second set of values for timing in early and late conditions, which are created by linear interpolation between the simulated endpoints. With the above-described approach, the number of data points requiring testing can be immense. Some approaches also use simulation tolerances including separate, independent variations of the dielectric thickness between wire levels, thus increasing the number of process variations. In any event, resistance and capacitance are calculated for each set of geometries. The designed circuit interconnect structures define the target geometry. Finally, the resistance and capacitance values (non-Gaussian distributions) for the circuit are then used for statistical timing. Unfortunately, the above-described approaches do not minimize the number of parameters necessary, and thus are still very cumbersome.
In view of the foregoing, a need exists in the art for an improved approach for forming a statistical model of independently variable parameters for timing analysis.